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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-10142-4E
MEMORY
CMOS 4 M x 1 BIT FAST PAGE MODE DRAM MB814100A-60/-70/-80
CMOS 4,194,304 x 1 bit Fast Page Mode Dynamic RAM s DESCRIPTION
The Fujitsu MB814100A is a fully decoded CMOS Dynamic RAM (DRAM) that contains a total of 4,194,304 memory cells in a x1 configuration. The MB814100A features a "fast page" mode of operation whereby highspeed random access of up to 2,048-bits of data within the same row can be selected. The MB814100A DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. Since the standby current of the MB814100A is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. The MB814100A is fabricated using silicon gate CMOS and Fujitsu's advanced four-layer polysilicon process. This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for the MB814100A are not critical and all inputs are TTL compatible.
s PRODUCT LINE & FEATURES
Parameter RAS Access Time CAS Access Time Address Access Time Randam Cycle Time Fast Page Mode Cycle Time Low Power Dissipation Operating current Standby current MB814100A-60 60 ns max. 15 ns max. 30 ns max. 110 ns min. 40 ns min. 605 mW max. MB814100A-70 70 ns max. 20 ns max. 35 ns max. 125 ns min. 45 ns min. 550 mW max. MB814100A-80 80 ns max. 20 ns max. 40 ns max. 140 ns min. 45 ns min. 495 mW max.
11 mW max. (TTL level) / 5.5 mW max. (CMOS level) * RAS only, CAS-before-RAS, or Hidden Refresh * Fast page Mode, Read-Modify-Write capability * On chip substrate bias generator for high performance
* 4,194,304 words x1 bit organization * Silicon gate, CMOS, 3D-Stacked Capacitor Cell * All input and output areTTL compatible * 1024 refresh cycles every16.4 ms * Common I/O capability by using early write
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
1
MB814100A-60/MB814100A-70/MB814100A-80
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage at any pin relative to VSS Voltage of VCC supply relative to VSS Power Dissipation Short Circuit Output Current Storage Temperature Symbol VIN, VOUT VCC PD -- TSTG Value -1 to +7 -1 to +7 1.0 50 -55 to +125 Unit V V W mA C
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
s PACKAGE
Marking Side
LCC-26P-M04 ZIP-20P-M02
(Normal Bend)
Marking Side (Reverse Bend)
FPT-26P-M01
FPT-26P-M02
Package and Ordering Information
- 26-pin plastic (300 mil) SOJ, order as MB814100A-xxPJN - 20-pin plastic ZIP, order as MB814100A-xxPZ - 26-pin plastic (300 mil) TSOP, with normal bend leads, order as MB814100A-xxPFTN - 26-pin plastic (300 mil) TSOP, with reverse bend leads, order as MB814100A-xxPFTN
2
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 1 - MB814100A DYNAMIC RAM - BLOCK DIAGRAM
RAS CAS
Clock Gen #1 Write Clock Gen Mode Control
WE
Clock Gen #2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
Refresh Address Counter Substrate Bias Gen Address Buffer & PreDecoder Row Decoder
Data In Buffer
DIN
Column Decoder Sense Ampl & I/O Gate
4,194,304 Bit Storage Cell
Data Out Buffer
DOUT
VCC VSS
s CAPACITANCE
(TA=25C, F=1 MHZ)
Parameter Input Capacitance, A0 to A10, DIN Input Capacitance, RAS, CAS, WE Input Capacitance, DOUT
Symbol CIN1 CIN2 COUT
Typ. -- -- --
Max. 5 7 7
Unit pF pF pF
3
MB814100A-60/MB814100A-70/MB814100A-80
s PIN ASSIGNMENT AND DESCRIPTION
26-Pin SOJ:
(Top View) DIN WE RAS N.C. A10
1 2 3 4 5 26 25 24 23 22
26-Pin FPT:
(Top View) VSS DOUT CAS N.C. A9 DIN WE RAS N.C. A10
1 2 3 4 5 26 25 24 23 22
VSS DOUT CAS N.C. A9
A0 A1 A2 A3 VCC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
A0 A1 A2 A3 VCC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
20-Pin ZIP: (Top View)
CAS
2 1 3
VSS WE A10 N.C. A1 A3
4 5 6 7 8 9 10 11 12 13 14 15
A4
16 17 18
A6
20 19
A8
VSS DOUT CAS N.C. A9
26 25 24 23 22 1 2 3 4 5
A9 DOUT DIN RAS N.C. A0
A2
VCC A5
A7
DIN WE RAS N.C. A10
Designator DIN DOUT WE RAS N.C. A0 to A10 VCC CAS VSS Data Input.
Function
Data Output. Write Enable. Row Address Strobe. No Connection. Address Inputs. +5 volt Power Supply. Column Address Strobe. Circuit Ground.
A8 A7 A6 A5 A4
18 17 16 15 14
9 10 11 12 13
A0 A1 A2 A3 VCC
4
MB814100A-60/MB814100A-70/MB814100A-80
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs Notes 1 1 1 Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -2.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 Unit V V V 0C to +70C Ambient Operating Temp
s FUNCTIONAL OPERATION
ADDRESS INPUTS Twenty-two input bits are required to decode any one of 4,194,304 cell addresses in the memory matrix. Since only eleven address bits (A0-A10) are available, the column and row inputs are separately strobed by RAS and CAS as shown in Figure 5. First, eleven row address bits are applied on pins A0-through-A10 and latched with the row address strobe (RAS) then, eleven column address bits are applied and latched with the column address strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively. The address latches are of the flow-through type; thus, address information appearing after tRAH (min.)+ tT is automatically treated as the column address. WRITE ENABLE The read or write mode is determined by the logic state of WE . When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored. DATA INPUT Input data is written into memory in either of two basic ways--an early write cycle and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data is strobed by CAS and the setup/hold times are referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal. DATA OUTPUT The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: tRAC : tCAC : tAA : from the falling edge of RAS when tRCD (max.) is satisfied. from the falling edge of CAS when tRCD is greater than tRCD (max.). from column address input when tRAD is greater than tRAD (max.).
The data remains valid until either CAS returns to a High logic level. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. FAST PAGE MODE OF OPERATION The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each fast page of memory, any of 2,048-bits can be accessed and, when multiple MB 814100s are used, CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read, write, and/or ready-modify-write cycles are permitted.
5
MB814100A-60/MB814100A-70/MB814100A-80
s DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter Output High Voltage Output Low Voltage Notes 1 1 Symbol VOH VOL Conditions IOH = -5 mA IOL = 4.2 mA 0 VVIN5.5 V; 4.5 VVCC5.5 V; VSS =0 V; All other pins not under test = 0 V 0 VVOUT5.5 V; Data out disabled RAS & CAS cycling; tRC = min. RAS = CAS = VIH ICC2 RAS = CAS VCC -0.2 V CAS = VIH, RAS cycling; tRC = min. -- --
Note 3
Values Min. 2.4 -- Typ. -- -- Max. -- V 0.4 Unit
Input Leakage Current (Any input)
II(L)
-10
--
10 A
Output Leakage Current Operating current (Average Power Supply Current) 2 Standby Current (Power Supply Current) Refresh Current #1 (Average Power Supply Current) 2 Fast Page Mode Current MB814100A-60 MB814100A-70 MB814100A-80 TTL Level CMOS level MB814100A-60 MB814100A-70 MB814100A-80 MB814100A-60 2 MB814100A-70 MB814100A-80 Refresh Current #2 (Average Power Supply Current) 2 MB814100A-60 MB814100A-70 MB814100A-80
IO(L)
-10
--
10 110
ICC1
--
--
100 90 2.0 1.0 110
mA
mA
ICC3
--
--
100 90 55
mA
ICC4
RAS =VIL, CAS cycling; tRC = min.
--
--
50 45 90
mA
ICC5
RAS cycling; CAS-before-RAS; tRC = min.
--
--
80 70
mA
6
MB814100A-60/MB814100A-70/MB814100A-80
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5
No. 1 2 3 4 5 6 7 8 9 Parameter Time Between Refresh Random Read/Write Cycle Time Read-Modify-WriteCycle Time Access Time from RAS Access Time from CAS Column Address Access Time Output Hold Time Output Buffer Turn On Delay Time Output Buffer Turn off Delay Time 10 6,9 7,9 8,9 Notes Symbol tREF tRC tRWC tRAC tCAC tAA tOH tON tOFF tT tRP tRAS tRSH tCRP 11,12 tRCD tCAS tCSH 17 tCPN tASR tRAH tASC tCAH 13 tRAD tRAL tCAL tRCS 14 tRRH MB814100A-60 MB814100A-70 MB814100A-80 Min. -- 110 130 -- -- -- 0 0 -- 2 40 60 15 5 20 15 60 10 0 10 0 12 15 30 30 0 0 Max. 16.4 -- -- 60 15 30 -- -- 15 50 -- 100000 -- -- 45 -- -- -- -- -- -- -- 30 -- -- -- -- Min. -- 125 150 -- -- -- 0 0 -- 2 45 70 20 5 20 20 70 10 0 10 0 12 15 35 35 0 0 Max. 16.4 -- -- 70 20 35 -- -- 15 50 -- 100000 -- -- 50 -- -- -- -- -- -- -- 35 -- -- -- -- Min. -- 140 165 -- -- -- 0 0 -- 2 50 80 20 5 20 20 80 10 0 10 0 15 15 40 40 0 0 Max. 16.4 -- -- 80 20 40 -- -- 20 50 -- 100000 -- -- 60 -- -- -- -- -- -- -- 40 -- -- -- -- Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10 Transition Time 11 RAS Precharge Time 12 RAS Pulse Width 13 RAS Hold Time 14 CAS to RAS Precharge Time 15 RAS to CAS Delay Time 16 CAS Pulse Width 17 CAS Hold Time 18 CAS Precharge Time (Normal)
19 Row Address Set Up Time 20 Row Address Hold Time 21 Column Address Set Up Time 22 Column Address Hold Time 23 RAS to Column Address Delay Time
24 Column Address to RAS Lead Time 25 Column Address to CAS Lead time 26 Read Command Set Up Time 27 Read Command Hold Time Referenced to RAS
7
MB814100A-60/MB814100A-70/MB814100A-80
s AC CHARACTERISTICS (Continued)
(At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5
No. 28 29 Parameter Read Command Hold Time Referenced to CAS Write Command Set Up Time Notes Symbol 14 15 tRCH tWCS tWCH tWP tRWL tCWL tDS tDH 15 15 15 tRWD tCWD tAWD tRPC tCSR tCHR tWSR tWHR tPC tPRWC 9,16 tCPA tCP tRASP tRHCP tCPWD MB814100A-60 MB814100A-70 MB814100A-80 Min. 0 0 10 10 15 15 0 10 60 15 30 0 0 10 0 10 40 60 -- 10 -- 35 35 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 -- 200000 -- -- Min. 0 0 10 10 20 18 0 10 70 20 35 0 0 10 0 10 45 68 -- 10 -- 40 40 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40 -- 200000 -- -- Min. 0 0 12 12 20 20 0 12 80 20 40 0 0 12 0 10 45 70 -- 10 -- 40 40 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40 -- 200000 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
30 Write Command Hold Time 31 WE Pulse Width 32 Write Command to RAS Lead Time 33 Write Command to CAS Lead Time 34 DIN set Up Time 35 DIN Hold Time 36 RAS to WE Delay Time 37 CAS to WE Delay Time 38 39 40 41 Column Address to WE Delay Time
RAS Precharge time to CAS Active Time (Refresh cycles) CAS Set Up Time for CAS-beforeRAS Refresh CAS Hold Time for CAS-beforeRAS Refresh 18 18
42 WE Set Up Time from RAS 43 WE Hold Time from RAS 51 52 53 54 Fast Page Mode Read/Write Cycle Time Fast Page Mode Read-ModifyWrite Cycle Time Access Time from CAS Precharge
Fast Page Mode CAS Precharge Time Fast Page Mode RAS Hold Time from CAS Precharge Fast Page Mode CAS Precharge to WE Delay Time
55 Fast Page Mode RAS Pulse width 56 57
8
MB814100A-60/MB814100A-70/MB814100A-80
Notes: 1. Referenced to VSS 2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the output open. ICC depends on the number of address change as RAS = VIL and CAS = VIH. ICC1, ICC3 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC4 is specified at one time of address change during one Page Cycle. 3. An Initial pause (RAS=CAS=VIH) of 200 s is required after power-up followed by any eight RAS-only cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 4. AC characteristics assume tT = 5 ns. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also transition times are measured between VIH (min.) and VIL (max.). 6. Assumes that tRCD tRCD (max.), tRAD tRAD (max.). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig. 2 and 3. 7. If tRCD tRCD (max.), tRAD tRAD(max.), and tASC tAA- tCAC - tT, access time is tCAC. 8. If tRAD tRAD (max.) and tASC tAA- tCAC - tT, access time is tAA. 9. Measured with a load equivalent to two TTL loads and 100 pF. 10. tOFF is specified that output buffer change to high impedance state. 11. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only; if tRCD is greater than the specified tRCD (max.) limit, access time is controlled exclusively by tCAC or tAA. 12. tRCD (min.) = tRAH (min.)+ 2tT + tASC (min.). 13. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only; if tRAD is greater than the specified tRAD (max.) limit, access time is controlled exclusively by tCAC or tAA. 14. Either tRRH or tRCH must be satisfied for a read cycle. 15. tWCS, tCWD , tRWD and tAWD are not a restrictive operating parameter. They are included in the data sheet as an electrical characteristic only. If tWCS t WCS (min.), the cycle is an early write cycle and Dout pin will maintain high impedance state thoughout the entire cycle. If tCWD tCWD (min.), tRWD tRWD (min.), and tAWD tAWD(min.), the cycle is a read modify-write cycle and data from the selected cell will apper at the Dout pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data will appear the Dout pin , and write operation can be exected by satisfying tRWL , tCWL, tCAL and tRAL specifications. 16. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H"). Therefore, if tCP is long, tCPA is longer than tCPA (max.). 17. Assumes that CAS-before- RAS refresh. 18. Assumes that Test mode function.
9
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 2 - tRAC vs. tRCD
tRAC (ns) tRAC (ns)
Fig. 3 - tRAC vs. tRAD
tCPA (ns) 80
Fig. 4 - tCPA vs. tCP
140 120 100 80 60 40
80 ns Version 70 ns Version 60 ns Version
100 70 90
80 ns Version
60 50 40 30
70 ns/80 ns Version 60 ns Version
80
70 ns Version
70
60 ns Version
60 50
20
40
60 80 100 120 tRCD (ns)
10
20
30 40 50 tRAD (ns)
60
10
20
30 40 tCP (ns)
50
60
s FUNCTIONAL TRUTH TABLE
Operation Mode Standby Read Cycle Write Cycle (Early Write) Read-ModifyWrite Cycle RAS-only Refresh Cycle CAS-before-RAS Refresh Cycle Hidden Refresh Cycle Test mode set cycle (CBR) Test mode set cycle (Hidden) Clock Input RAS H L L L L L HL L HL CAS H L L L H L L L L WE X H L HL X H H L L Address Input Row -- Valid Valid Valid Valid -- -- -- -- Column -- Valid Valid Valid -- -- -- -- -- Input -- -- Valid X Valid -- -- -- -- -- Data Output High-Z Valid High-Z Valid High-Z High-Z Valid High-Z Valid Refresh -- Yes *1 Yes *1 Yes *1 Yes Yes Yes Yes Yes tCSR tCSR (min.) Previous data is kept tCSR tCSR (min.) tWSR tWSR (min.)
CSR tCSR (min.) tWSR tWSR (min.)
Note
tRCS tRCS (min.) tWCS tWCS (min.) tCWD tCWD (min.)
Note : X : "H" or "L" *1: It is impossible in Fast Page Mode.
10
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 5 - READ CYCLE
tRC tRAS RAS VIH VIL tCRP tRCD CAS VIH VIL tASR VIH VIL tRAH tCSH tRSH tCAS tRAD tRAL tASC tCAL tCAH
COLUMN ADD
tRP
A0 to A10
ROW ADD
tRCS VIH VIL tRAC VOH DOUT VOL
HIGH-Z VALID DATA
tRRH tRCH tAA tCAC tOH tOFF
HIGH-Z
WE
tON
"H" or "L"
Invalid Data
DESCRIPTION The read cycle is executed by keeping both RAS and CAS "L" and keeping WE "H" throughout the cycle. The row and column addresses are latched with RAS and CAS, respectively. The data output remains valid with CAS "L", i.e., if CAS goes "H" , the data becomes invalid after tOH is satisfied. The access time is determined by RAS (tRAC), CAS (tCAC), or Column address input (tAA). If tRCD (RAS to CAS delay time) is greater than the specification, the access time is tAA.
11
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 6 - WRITE CYCLE (Early Write)
tRC tRAS RAS VIH VIL tCSH tCRP tRCD CAS VIH VIL tASR tRAD tRAH tASC A0 to A10 VIH VIL
ROW ADD COLUMN ADD
tRSH tCAS
tRP
tRAL tCAH tCAL
tWCS WE VIH VIL
tWCH
tDS DIN VIH VIL
tDH
VALID DATA IN
DOUT
VOH VOL
HIGH-Z
"H" or "L" DESCRIPTION The write cycle is executed by the same manner as read cycle except for the state of WE and DIN pins. The data on DIN pin is latched with the later falling edge of CAS or WE and written into memory. In addition, during write cycle, tRWL and tRAL must be satisfied with the specifications.
12
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 7 - READ WRITE/READ-MODIFY-WRITE CYCLE
tRWC tRAS RAS VIH VIL tCSH tCRP VIH VIL tASR tRAH VIH VIL tRCD tCAS tRAD tASC tAWD tCAH A0 to A10
ROW ADD. COLUMN ADDRESS
tRP
tRSH
CAS
tRAL tCWL tRWL
tRCS
tCWD tWP
WE
VIH VIL tRWD tDS tDH VIH VIL tCAC tAA
tRAC
DIN
VALID DATA
tOFF tOH
VOH DOUT VOL
HIGH-Z
VALID DATA
tON
"H" or "L"
Invalid Data DESCRIPTION The read-modify-write cycle is executed by changing WE from "H" to "L" after the data appears on the DOUT pin. After the current data is read out, modified data can be rewritten into the same address quickly.
13
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 8 - FAST PAGE MODE READ CYCLE
tRASP RAS VIH VIL tPC tCRP
tRCD
tRHCP tRP tRSH tCP tCAS tCAS tCAS
tCSH
CAS
VIH VIL tASR
tRAD tCAH tRAH tASC tCAH tASC tASC tRAL tCAH
A0 to A10
VIH VIL
ROW ADD
COL ADD
COL ADD
COL ADD
tRCS
tRCS tRCH tRRH
tRCH
WE
VIH VIL tON tAA tCPA tCAC tON tOFF
tCAC tAA tRAC VOH DOUT VOL
HIGH-Z
tOH tOFF
tOH
VALID
VALID
VALID
DESCRIPTION The fast page mode read cycle is executed after normal cycle with holding RAS "L", applying column address and CAS, and keeping WE "H" . Once an address is selected normally using the RAS and CAS, other addresses in the same row can be selected by only changing the column address and applying the CAS. During fast page mode, the access time is tCAC, tAA, or tCPA, whichever occurs later. Any of the 2048 bits belonging to each row can be accessed.
14
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 9 - FAST PAGE MODE WRITE CYCLE (Early Write)
tRASP RAS VIH VIL tCSH tCRP tRCD CAS VIH VIL tRAH tASR VIH A0 to A10 VIL
ROW ADD
tRHCP tRSH tPC tCAS tCP tCAS tCAS tRP
tRAD tCAH tASC
COL ADD
tASC
tCAH tCAL
COL ADD
tCAH tRAL tASC
COL ADD
tWCS
tWCH tCWL tWCS tCWL
tWCH tWCS tWCH tCWL
WE
VIH VIL tWP tDS tDH
VALID DATA
tWP tDS
VALID DATA
tWP tRWL tDH tDS tDH
VALID DATA
DIN
VIH VIL
DOUT
VOH VOL
HIGH-Z
"H" or "L"
DESCRIPTION The fast page mode write cycle is executed by the same manner as fast page mode read cycle except for the state of WE. The data on DIN pin is latched with the falling edge of CAS and written into the memory. During fast page mode write cycle, tCWL must be satisfied. Any of the 2048 bits belonging to each row can be accessed.
15
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 10 - FAST PAGE MODE READ-MODIFY-WRITE CYCLE
RAS
VIH VIL tCRP tRCD tCAS VIH VIL tCSH tPRWC
tRASP tRP tCAS tRSH
CAS
tRAD tRAH tASR tASC
COLUMN ADDRESS
tCP tCAH tASC tRAH tRAL tCWL
COLUMN ADDRESS
A0 to A10
VIH VIL
ROW ADDR.
COLUMN ADDRESS
tRWD tAWD tRCS VIH VIL tCWD tWP WE
tCWL tCPWD tCWD
tCWL
tRWL
tWP
tWP
tDS tDH tDS VIH VIL tRAC tAA tCAC tOFF DOUT VOH VOL tON
VALID VALID VALID DATA
tDS
tDH
tDH
DIN
VALID
VALID
VALID
tAA tCPA tCAC tOFF
tCAC tAA
tOH
tON
tOH
tON
"H" or "L" Invalid Data
DESCRIPTION During fast page mode, the read-modify-write cycle can be executed by changing WE high to low after the data appears at DOUT pin as well as normal cycle. Any of the 2048 bits belonging to each row can be accessed.
16
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 11 - RAS-ONLY REFRESH (WE, DIN, A10 = "H" or "L")
tRC tRAS RAS VIH VIL tASR VIH A0 to A9 VIL tCRP CAS VIH VIL tOH DOUT VOH VOL
HIGH-Z "H" or "L"
tRP tRAH
ROW ADDRESS
tRPC
tOFF
DESCRIPTION
The refresh of DRAM is executed by normal read, write or read-modify-write cycle, i.e., the cells on the one row line are also refreshed by executing one of three cycles. 1024 row address must be refreshed every 16.4 ms period. During the refresh cycle, the cell data connected to the selected row are sent to sense amplifier and re-written to the cell. The MB814100A has three types of refresh modes, RAS-only refresh, CAS-before-RAS refresh, and Hidden refresh. The RAS only refresh is executed by keeping RAS "L" and CAS "H" throughout the cycle. The row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, the DOUT pin is kept in a high impedance state.
Fig. 12 - CAS-BEFORE-RAS REFRESH (A0 to A10, DIN = "H" or "L")
tRC RAS VIH VIL tCPN WE VIH VIL tWSR CAS VIH VIL tOFF tOH DOUT VOH VOL
HIGH-Z
tRAS tCSR
tRP
tCHR
tRPC
tWHR
"H" or "L" DESCRIPTION The CAS-before-RAS refresh is executed by bringing CAS "L" before RAS. By this timing combination, the MB814100A executes CASbefore-RAS refresh. The row address input is not necessary because it is generated internally. WE must be held "H" for the specified set up time (tWSR) before RAS goes "L" in order not to enter "test mode".
17
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 13 - HIDDEN REFRESH CYCLE
tRC tRAS RAS VIH VIL tCRP CAS VIH VIL tASR A0 to A10 VIH VIL tRCD tRAD tRAH tASC tRAL tCAH
COLUMN ADD.
tRC tRP tRAS tRP
tRSH tCHR
ROW ADDRESS
[Normal mode]
WE
(Read)
tRCS tCAC tRAC tON tRWD tCWD tRCS tAWD tAA
tRRH
tWSR
tWHR
VIH VIL
tOH
VALID DATA
tOFF
DOUT
VOH VOL
HIGH-Z
tWP
tWSR
tWHR
(Read/Write VIL Cycle)
WE
VIH tDS
tDH
VALID
DIN
VIH VIL tRCS tCAC tAA tRAC tON
HIGH-Z
[Test mode]
WE
(Read)
tWSR
tWHR
VIH VIL
tOH
VALID DATA
tOFF
DOUT
VOH VOL VIH
tRWD tRCS tCWD tAWD tDS
VALID
tWP
tWSR
tWHR
(Read/Write VIL Cycle)
WE
tDH
DIN
VIH VIL
DESCRIPTION
"H" or "L"
The hidden refresh is executed by keeping CAS "L" to next cycle, i.e., the output data at previous cycle is kept during next refresh cycle. Since the CAS is kept low continuously from previous cycle, followed refresh cycle should be CAS-before-RAS refresh. WE must be held "H" for the specified set up time (tWSR) before RAS goes "L" for the secound time in order not to enter "test mode" to be specified later.
18
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 14 - TEST MODE SET CYCLE (A0 to A10, DIN = "H" or "L")
tRC VIH VIL tRAS tRP
RAS
tCPN VIH VIL
tCSR
tRPC tCHR
CAS
tWSR WE VIH VIL tOFF tOH DOUT VOH VOL
tWHR
HIGH-Z
"H" or "L"
DESCRIPTION Test Mode ; The purpose of this test mode is to reduce device test time to one eighth of that required to test the device conventionally. The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle. In the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of RA10, CA0 and CA10. In the write mode, data at DIN is written into eight cells simultaneously. In the read mode, eight cells at the selected addresses are read back and checked in the following manner. When the eight bits are all "L" or all "H", a "H" level is output. When the eight bits show a combination of "L" and "H", a "L" level is output. The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle. In test mode operation, the following parameters are delayed approximately 5ns from the specified value in the data sheet. tRC, tRWC, tRAC, tAA, tRAS, tCSH, tRAL, tRWD, tAWD, tPC, tPRWC, tCPA, tRHCP, tCPWD
19
MB814100A-60/MB814100A-70/MB814100A-80
Fig. 15 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
VIH VIL VIH VIL tCSR
RAS
tCHR
tCP
tFRSH tFCAS tFCAH tRAL
tRP
CAS
VIH A0 to A10 VIL tWSR WE
(Read)
tASC tWHR tRSC
COLUMN ADDRESS
tRRH tFCAC tON
HIGH-Z
VIH VIL VOH VOL VIH VIL VOH VOL tRCS
tRCH tOH
VALID DATA
tOFF
DOUT WE
(Write)
tFCWD
tCWL tRWL tWP tDH
VALID DATA "H" or "L"
tDS DIN
DESCRIPTION A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle. CAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Address: Bits A0 through A10 are defined by the on-chip refresh counter. Column Address: Bits A0 through A10 are defined by latching levels on A0-A9 at the second falling edge of CAS. The CAS-before-RAS Counter Test procedure is as follows ; 1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles. 2) Use the same column address throughout the test. 3) Write "0" to all 1024 row addresses at the same column address by using normal write cycles. 4) Read "0" written in procedure 3) and check; simultaneously write "1" to the same addresses by using CAS-before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 1024 times with addresses generated by the internal refresh address counter. 5) Read and check data written in procedure 4) by using normal read cycle for all 1024 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). (At recommended operating conditions unless otherwise noted.) No. 90 90 92 93 94 Note: Parameter Access Time from CAS Column Address Hold CAS to WE Delay CAS Puls width RAS Hold Time Symbol tFCAC tFCAH tFCWD tFCAS tFRSH MB814100A-60 Min. Max. -- 30 50 50 50 50 -- -- -- -- MB814100A-70 Min. Max. -- 30 55 55 55 55 -- -- -- -- MB814100A-80 Min. Max. -- 35 60 60 60 60 -- -- -- -- Unit ns ns ns ns ns
Assumes that CAS-before-RAS refresh counter test cycle only.
20
MB814100A-60/MB814100A-70/MB814100A-80
s PACKAGE DIMENTIONS
(Suffix: -PJN)
26 pin, Plastic SOJ (LCC-26P-M04)
3.40 -0.20 .134 -.008 * 17.150.13(.675.005)
22 26 18 14
+0.35 +.014
2.25(.089)NOM 0.64(.025)MIN R0.81(.032)TYP
INDEX
7.62 (.300) 8.430.13 (.332.005) NOM
6.810.51 (.268.020)
LEAD No
1 5 9 13
0.20 -0.02 .008 -.001
+0.05
+.002
1.27(.050)TYP
2.54(.100)TYP 15.24(.600)REF 2.50(.098)NOM
Details of "A" part 0.81(.032)MAX
0.10(.004)
"A"
0.430.10(.017.004)
C
1995 FUJITSU LIMITED C26054S-3C-1
Dimensions in mm(inches).
21
MB814100A-60/MB814100A-70/MB814100A-80
s PACKAGE DIMENSIONS (Continued)
(Suffix: -PZ)
20 pin, Plastic ZIP (ZIP-20P-M02)
25.88 -0.30 1.019 -.012
+0.20 +.008
2.850.20 (.112.008)
INDEX
8.500.25 (.335.010)
9.830.33 (.387.013)
0.250.05 (.010.002)
3.00(.118)MIN
1.27(.050)TYP LEAD No.
1
0.500.10(.020.004)
2.54(.100)TYP
(BOTTOM VIEW)
20
C
1994 FUJITSU LIMITED Z20002S-4C-2
Dimensions in mm(inches).
22
MB814100A-60/MB814100A-70/MB814100A-80
s PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTN)
26 pin, Plastic TSOP(II) (FPT-26P-M01)
Details of "A" part
26 22 18 14
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.50(.020)MAX LEAD No.
1 5 9 13
* 17.140.10
(.675.004) 0.400.10 (.016.004) 0.21(.008)
M
1.10 -0.05 +.004 .043 -.002
+0.10
9.220.20 (.363.008) 7.620.10 (.300.004)
0.150.05 (.006.002)
1.27(.050)TYP
0.10(.004) 15.24(.600)REF
0(0)MIN (STAND OFF)
0.500.10 (.020.004)
8.220.20 (.324.008)
C
1994 FUJITSU LIMITED F26001S-3C-3
Dimensions in mm(inches).
23
MB814100A-60/MB814100A-70/MB814100A-80
s PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTR)
26 pin, Plastic TSOP(II) (FPT-26P-M02)
Details of "A" part
26 22 18 14
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.50(.020)MAX LEAD No.
1 5 9 13
15.24(.600)REF 1.27(.050)TYP 0.10(.004) 0(0)MIN (STAND OFF) 0.500.10 (.020.004) 8.220.20 (.324.008) 0.150.05 (.006.002)
0.400.10 (.016.004)
0.21(.008)
M
1.10 -0.05 +.004 .043 -.002
+0.10
*17.140.10
(.675.004)
7.620.10 (.300.004) 9.220.20 (.363.008)
C
1994 FUJITSU LIMITED F26002S-3C-3
Dimensions in mm(inches).
24
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
24

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